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STLC1
LED LAMPS CLUSTER DRIVER
s
s
s
s s s s
FULLY MONOLITHIC FIXED FREQUENCY SMPS THREE LOW SIDE DRIVERS FOR STOP TAIL AND TURN LED LAMPS ARRAYS DRIVING PROGRAMMABLE LOW SIDE DRIVER OVER CURRENT LIMIT PROTECTION UNDER CURRENT DIAGNOSTIC INPUT OVERVOLTAGE PROTECTION VERY LOW STAND-BY CURRENT THERMAL PROTECTION WITH HYSTERESIS
PowerSO-20TM
DESCRIPTION The STLC1, a device realized with the well established BCD technology, is a fixed frequency fully monolithic SMPS, with three independent smart low side driver, primarily intended for automotive rear led lamps driving. SCHEMATIC DIAGRAM
B+ OSCILLATOR
The output voltage is set using a simple resistor divider. Thermal shutdown with hysteresis, input over-voltage and overcurrent protections give robust design solutions.
THERMAL PROTECTION P-OUT PWM SWITCH CONTOLLER COMP1 + Rs
TURN STOP TAIL
I N P U T
CNTL TS -PWM PWM COMP
ERR AMP
1.24V +
FDBK
PULSE WIDTH CONTROLLER
REF
REF TR -DRV
OSC
M1 ST -DRV
GND
M2 TL -DRV M3 LAMP OUTAGE DETECT TL -L ST -L TR -L
LMP -OUT
September 2002
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STLC1
ABSOLUTE MAXIMUM RATINGS
Symbol VB+ VB+ VTURN, VSTOP, VTAIL ITURN, ISTOP, ITAIL ITR-DRV, ITL-DRV, IST-DRV ILMP-OUT VP-OUT IP-OUT Tstg TJ Operating Supply Voltage TURN, STOP and TAIL input pins voltage Parameter Transient Supply Voltage (load dump) Value 60 24 VB+ + 0.3 Unit V V V
TURN, STOP and TAIL pins current
10
mA
TR-DRV, TL-DRV and ST-DRV pins sink current
1.5
A
LMP-OUT pin sink current P-OUT DC Voltage P-OUT pin sink current Storage Temperature Range Operating Junction Temperature Range
120 60 Internally Limited -55 to +150 -40 to +125
mA V A C C
THERMAL DATA
Symbol Rthj-case Rthj-amb Parameter Thermal Resistance Junction-case Thermal Resistance Junction-Ambient PowerSO-20TM 2 50 Unit C/W C/W
CONNECTION DIAGRAM (top view)
PowerSO-20TM
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STLC1
PIN DESCRIPTION
Pin N 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Symbol GND TR-DRV TR-L ST-DRV ST-L TL-DRV TL-L CNTL REF GND GND B+ TAIL STOP TURN FDBK P-OUT TS-PWM LMP-OUT GND Name and Function Ground The Low Side Driver drain pin for the TURN LED array The Low Side Driver source pin, used to detect either a lamp outage or an over-current condition for the TURN LED array The Low Side Driver drain pin for the STOP LED array The Low Side Driver source pin, used to detect either a lamp outage or an over-current condition for the STOP LED array The Low Side Driver drain pin for the TAIL LED array The Low Side Driver source pin, used to detect either a lamp outage or an over-current condition for the TAIL LED array Determines, according to a percentange of VREF, the Pulse Width Controller internal oscillator duty cycle Stable Reference Voltage Ground Ground Power Supply TAIL input pin. When brought high, TAIL activates the IC and drives the TAIL led array. STOP input pin. When brought high, STOP activates the IC and drives the STOP led array. TURN input pin. When brought high, TURN activates the IC and drives the TURN led array. Internal Error Amplifier Inverting Pin Power MOSFET drain pin A Three State Input. It determine the control logic for TAIL and STOP Low Side Drivers. A weak pulled up signal during lamps No Fault condition and an active pulldown when a Fault condition is detected. Ground
ORDERING INFORMATION
TYPE STLC1 PowerSO-20TM STLC1PD
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STLC1
TYPICAL APPLICATION CIRCUIT
Iout
OUT TAIL TURN COUT RF1
STOP RLR RLS RLT RTR RTS RTT
GND TR-DRV TR-L ST-DRV ST-L TL-DRV TL-L CNTL REF
GND LMP-OUT TS-PWM P-OUT FDBK TURN STOP TAIL B+ GND
RF2 CSEPIC
IP-OUT
RC1
RC2
CREF
GND
ELECTRICAL CHARACTERISTICS FOR SMPD SECTION (TJ=-40 to 125C unless otherwise specified. Typical values are referred at TJ=25C, VB+=14V)
Symbol VB+ VSD ISQ fosc RP(on) Parameter Supply Operating Voltage B+ Input Overvoltage Shutdown Total Off State Quiescent Current Test Conditions Normal Operating Range Normal Operating Range - TAIL only Min. 9 6 28 Typ. Max. 24 24 32 180 240 Unit V V A kHz m m 20 VFDBK = 1V 8 12 1.6 60 15 16 A A ms mV mV
30 120
VB+ = 14V, =0V PWM Oscillator Frequency VB+ = 14V Static drain to ground SMPS N-channel switch on resistance P-OUT Off State leakage Current IP-OUT Current Limit SMPS Turn On Delay Load Regulation Line Regulation VB+ = 9V, VB+ = 14V, VB+ = 16V, VB+ = 14V,
VTURN = VSTOP = VTAIL 140 IP-OUT=4A IP-OUT=4A
180 180 170
ID(off) ILIMIT tSMPS-ON VLOAD VLINE
CREF = 1F (see note 1,4 and Fig 1, 2) VB+ = 14V, IOUT = 0.6 to 3A VOUT = 10V VB+ = 9 to 16V, IOUT = 1.5A VOUT = 10V
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STLC1
ELECTRICAL CHARACTERISTICS FOR LOW SIDE DRIVER SECTION (TJ=-40 to 125C unless otherwise specified. Typical values are referred at TJ=25C, VB+=14V)
Symbol R(on) Parameter Static drain to source LSD N-channel switch on resistance VB+ = 9V, Test Conditions VTURN = VB+ VTR-L = 0V ITR-DRV=1A VSTOP = VB+ VST-L = 0V IST-DRV=1A VTAIL = VB+ ITL-DRV=1A ILSD(off) tLSD-ON VLS-ON VLS-OFF fLSD OFF State LSD'S leakage current LSD Turn On Delay FDBK Voltage over which LSD's are enabled FDBK Voltage over which LSD's are disabled Pulse Width Controller Internal Oscillator Frequency Input Threshold voltage to enable LSD Input Threshold voltage to disable LSD VTL-L = 0V Min. Typ. 500 500 500 10 2 0.95VFB 0.5VFB VTAIL = VB+ VTS-PWM = VREF/2 200 380 500 Max. Unit m m m A ms V V Hz
VTURN = VSTOP = VTAIL =0V VTR-DRV = VST-DRV = VTL-DRV = VB+ CREF = 1F COUT = 220F (see note 2,4 and Fig 1, 2)
VIN(ON) VIN(OFF)
VB+ = 9 to 16V VB+ = 9 to 16V
0.6VB+ 0.4VB+
V V
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STLC1
ELECTRICAL CHARACTERISTICS FOR FEEDBACK AND CONTROL (TJ=-40 to 125C unless otherwise specified. Typical values are referred at TJ=25C, VB+=14V)
Symbol VLOUT VH-SHORT VREF VFB Parameter Lamp Outage Detect Threshold Voltage Output Overcurrent Threshold Voltage External Voltage Reference Internal Band-gap Voltage Reference (see schematic diagram) Device Enabled Lamp Outage no fault High Voltage Device Disabled Lamp Outage no fault High Voltage Lamp Outage fault Low Voltage TJ=25C TJ=25C VTURN = VSTOP = VTAIL = VB+ IREF = 500A VTURN = VSTOP =VTAIL = VB+ Test Conditions Min. 150 1.2 3.6 1.15 Typ. 200 1.3 3.8 1.24 Max. 250 1.6 4 1.3 Unit mV V V V
VLH(en)
VLH(dis)
VB+ = 9 to 16V, ILMP-OUT < -4mA least one input enabled. No fault condition. VB+ = 9 to 16V, ILMP-OUT < -2mA VTURN = VSTOP = VTAIL = 0V
At
VB+-2
VB+
V
VB+-2
VB+
V
VLL R(IN)
TURN, STOP and TAIL Input Resistance TSHDN Thermal Shutdown Threshold Thermal Shutdown THYST Hysteresis Time to Fault Indication tF(on) ON Time to Fault Indication tF(off) OFF VTS-PWM(L) TS-PWM Low State Voltage (see table 1) VTS-PWM(M) TS-PWM Mid State Voltage (see table 1) VTS-PWM(H) TS-PWM High State Voltage (see table 1)
VB+ = 9 to 16V ILMP-OUT < 100mA At least one input enabled. Fault condition. VB+ = 12V, (see Note 4) (see Note 4)
1.5 18.5 150 10 60 8 0.1VREF 0.21VREF 0.98VREF 0.79VREF
V k C C s ms V V V
Note 1: The device is powered. If only one of the three inputs is enabled (the remaining inputs are shorted to ground), tSMPS-ON is the time required for the OUT voltage to reach the10% of its own steady state value Note 2: The device is powered. If only one of the three inputs is brought high (the remaining inputs are shorted to ground), TLSD-ON is the time required for the current to flow in the enabled LSD Note 3: The device is powered and at least one input is enabled. If this input is disabled, T LSD-OFF is the time required for the current to become zero in the previously enabled LSD. Note 4: Guaranteed by design, not tested in production.
FUNCTIONAL DESCRIPTION SMPS The N-channel Power MOSFET is source grounded, thus it is possible to use any converter configuration with the power switch connected to ground. A SEPIC topology (Single Ended Primary Inductor Current) is shown in the typical application schematic. INPUTS PINS The IC's inputs are TURN, STOP and TAIL. If all inputs are disabled, SMPS and most of the
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internal control and diagnostic circuitry are not active. This is done in order to maintain the stand-by quiescent current at very low values. When only one of these inputs is put high (e.g connected to VB+), a device start-up phase begins. First the CREF capacitor is charged and, once the voltage on it has reached about 95% of its steady state value (VREF), the SMPS is enabled. In order to allow the output to reach the regulated voltage value faster, the LSD corresponding to the input enabled will conduct
STLC1
only when the OUT voltage is about 95% of its final value. Such a start-up phase takes place when only one input is enabled. LOW SIDE DRIVER: The purpose of the low side drivers is to connect the LED cluster to ground, creating a path for the current. Using external resistors, current flowing into the LED cluster is set according to the following formula: V OUT - V ARRAY I ARRAY = --------------------------------------------R T + R L + R ( on ) where (see typical application schematic): RL = R LT, RLS, or RLR RT = R TT, RTS, or RTR R(on) = Static drain to source LSD on resistance VOUT = Output Voltage VARRAY = Expected LED array voltage drop. LSD over-current protection and under-current diagnostic (see LAMP OUTAGE DETECTION section) is performed by sensing the voltage on resistors, when the corresponding LSD are enabled. If the voltage on exceeds VH-SHORT, the over-current protection acts by reducing the LSD average current by switching ON and OFF the LSD itself. LAMP OUTAGE DETECTION Resistors are used to sense the LED array current. In case one or more LEDs fail (open circuit) the current on the corresponding resistor will drop due to the increased LED array resistance. As soon as the voltage drop on is lower than VLOUT, a LED lamp fault condition is detected and the LMP-OUT pin becomes active (low). The LAMP-OUTAGE functionality is AND-ed with each input, that is a fault condition can be detected only when the LED arrays are enabled. DIMMING The dimming of the LED lamps can be obtained by using the internal PULSE WIDTH controller (it drives the LSD TAIL and STOP gates). The duty cycle of this internal oscillator (whose frequency is 380Hz typical) can be set, forcing the voltage of the CNTL pin to be a fraction of VREF, by using a simple resistor divider (as shown in the typical application scheme). In this case the duty cycle percentage can be calculated with the following approximated formula:

R C1 0.2 3.8 if ---------------------------- ------------R C1 + R C2 V REF DC% R C1 ---------------------------- * 100 Elsewhere R C1 + R C2

The TS-PWM pin voltage, according to the TABLE1 determines which LSD is PULSE WIDTH CONTROLLER driven. Internal dimming can only be performed on the TAIL and STOP arrays. The TURN array can be externally dimmed (as well as TAIL and STOP) by driving the corresponding input witha a square pulse signal whose maximum frequency must be 200Hz.
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STLC1
TS-PWM ENCODING TABLE
DRIVE TYPE TYPE INPUTS ACTIVATED TAIL ARRAY LOW (VTS-PWM<0.1VREF) MID (VTS-PWM<0.1VREF/2 or floating) HIGH (VTS-PWM>0.98VREF) TAIL STOP TAIL AND STOP TAIL STOP TAIL AND STOP TAIL STOP TAIL AND STOP PWM OFF PWM PWM OFF PWM PWM ON ON STOP ARRY PWM ON ON OFF ON ON PWM ON ON
Figure 1 : Start-up phase and input signal timing diagram (with TS-PWM floating)
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STLC1
Figure 2 : Magnified start-up phase timing diagram
Figure 3 : Fault indication on and off timing diagram
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STLC1
TYPICAL CHARACTERISTICS (See PCB BOM) Figure 4 : Output Voltage vs Output Current Figure 7 : Output Voltage vs Output Current
Figure 5 : Output Voltage vs Output Current
Figure 8 : Duty Cycle Oscillator Frequency vs CNTL Voltage
Figure 6 : Output Voltage vs Output Current
Figure 9 : LMP-OUT Voltage (Fault Condition) vs LMP-OUT Sinked Current
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STLC1
Figure 10 : Total OFF State Quiescent Current vs Temperature Figure 13 : External Reference Voltage vs Temperature
Figure 11 : Time to Fault Indication ON vs Temperature
Figure 14 : VFB Voltage vs Temperature
Figure 12 : Time to Fault Indication OFF vs Temperature
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STLC1
Figure 15 : Demoboard Schematic
Figure 16 : PCB Components outline
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STLC1
Figure 17 : PBC Top Layer
Figure 18 : PBC Bottom Layer
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STLC1
PCB BOM
REFERENCE L1, L2 C4, C5, C6 C16 C7 C1, C2 C8, C9 C14 C18 C11 C12 R10 R11 R15 R16 R18 R12, R13, R14 R4, R6, R8 R5, R7, R9 TR1 RLP D1 DLP T1 JP1, JP2, JP3 DESCRIPTION VK200 22F-35V Electrolytic Capacitor Low ESR 220nF-35V Ceramic Capacitor X7R Dielectric 47F-35V Electrolytic Capacitor 4.7nF-35V Ceramic Capacitor X7R Dielectric 220F-35V Electrolytic Capacitor Low ESR 560pF 560pF-50V 1F-35V Tantalium Capacitor 220pF Ceramic Capacitor 9.1k Resistor 125mW 0.1% 1.3k Resistor 125mW 0.1% 4.7k Resistor 125mW 5% 56 Resistor 125mW 5% 10 Resistor 250mW 5% 1.2k Resistor 125mW 5% 2.2 Resistor 1W 5% 1 Resistor 1W 5% 10k Trimmer 1.5k Resistor 125mW 5% Schottky Diode STPS3L40S Led Diode SEPIC inductor, Toroid Horizontal THT 20H@10ADC, 200-250KHz Jumper
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STLC1
PowerSO-20 MECHANICAL DATA
DIM. A a1 a2 a3 b c D (1) E e e3 E1 (1) E2 G h L N S T 0 10.0 0.80 0 10.90 0 0.40 0.23 15.80 13.90 1.27 11.43 11.10 2.90 0.10 1.10 1.10 10 8 0 0.3937 0.0314 0.0000 0.4291 0.10 mm. MIN. TYP MAX. 3.60 0.30 3.30 0.10 0.53 0.32 16.00 14.50 0 0.0157 0.0090 0.6220 0.5472 0.0500 0.4500 0.4370 0.1141 0.0039 0.0433 0.0433 10 8 0.0039 MIN. inch TYP. MAX. 0.1417 0.0118 0.1299 0.0039 0.0209 0.0013 0.630 0.5710
(1) "D and E1" do not include mold flash or protusions - Mold flash or protusions shall not exceed 0.15mm (0.006")
N
N a2 A
R
c a1 DETAIL B E
b DETAIL A D e3
e
lea d
DETAIL A
20
11
a3 DETAIL B E2 T E1
Gage Plan e 0.35
slug
- C-
S
L
SEATI NG PLANE GC (COPLANARITY)
1
1
0
PSO20MEC
h x 45
0056635
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STLC1
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. (c) The ST logo is a registered trademark of STMicroelectronics (c) 2002 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. (c) http://www.st.com
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